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EDAC

32-BIT ERROR CODE DETECTION AND CORRECTION

Brief Description

This is a CMOS ASIC used to detect and correct soft and hard errors in memory devices used in control electronics for Fast Breeder Reactors.

ASIC designed by STARC based on Verilog HDL code provided by IGCAR.

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Specifications
  • Operating Freq: 16 MHz
  • I/O pins: 95
  • 3.3K Gate Count
  • Controls on/off operations of relays
  • Compatible with VME bus
  • - 40 C to + 85 C operation
  • Package: 208 PQFP
  • Application: Controlling Board relays in FBR electronics

Contacts

Semiconductor Technology and Applied Research Centre
(A unit of SITAR -Govt. of INDIA)
PO Box No.1640, off Old Madras Road,
Doorvani Nagar P.O.,
Bangalore 560 016, India.


Phone: 91 80 25653588
Fax: 91 80 25653590
Email: mail@sitarindia.com
URL: www.sitar.org.in